Surviving the Design of Microprocessor and Multimicroprocessor Systems: Lessons Learned

SURVIVING THE DESIGN OF MICROPROCESSOR AND MULTIMICROPROCESSOR SYSTEMS: LESSONS LEARNED......Page 1 PROLOGUE......Page 8 Foreword......Page 10 Preface......Page 11 Acknowledgments......Page 15 FACTS OF IMPORTANCE......Page 17 1. Basic Issues......Page 19 1.1. Pentium......Page 24 1.1.1. Cache and Cache Hierarchy......Page 27 1.1.3. Branch Prediction......Page 28 1.1.4. Input/Output......Page 29 1.1.6. Support for Shared Memory Multiprocessing......Page 30 1.1.7. Support for Distributed Shared Memory......Page 33 1.3. Pentium Pro......Page 34 1.4. Pentium II......Page 36 2. Advanced Issues......Page 37 3. About the Research of the Author and His Associates......Page 41 ISSUES OF IMPORTANCE......Page 43 1. Basic Issues......Page 45 1.2. Set-associative cache......Page 46 2. Advanced Issues......Page 47 3. About the Research of the Author and His Associates......Page 50 1. Basic Issues......Page 52 1.1. Example: MIPS R10000......Page 58 1.2. Example: DEC Alpha 21164......Page 60 2. Advanced Issues......Page 61 3. About the Research of the Author and His Associates......Page 66 1. Basic Issues......Page 68 1.1. Hardware BPS......Page 69 1.2. Software BPS......Page 78 1.3.1. Predicated Instructions......Page 79 1.3.2. Speculative Instructions......Page 80 2. Advanced Issues......Page 82 3. About the Research of the Author and His Associates......Page 88 1.1. Types of I/O Devices......Page 89 1.3. Storage System Design for Uniprocessors......Page 91 1.4. Storage System Design for Multiprocessor and Multicomputer Systems......Page 94 2.1. The Disk Cache Disk......Page 96 3. About the Research of the Author and His Associates......Page 97 1. Basic Issues......Page 98 1.1. Coarse Grained Multithreading......Page 99 1.2. Fine Grained Multithreading......Page 100 2. Advanced Issues......Page 102 3. About the Research of the Author and His Associates......Page 103 1. Basic Issues......Page 105 1.1. Snoopy Protocols......Page 106 1.1.1. Write-Invalidate Protocols......Page 107 1.1.3. MOESI Protocol......Page 108 1.2. Directory protocols......Page 109 1.2.1. Full-Map Directory Protocols......Page 111 1.2.2. Limited Directory Protocols......Page 112 1.2.2.2. The Dir(i)B Protocol......Page 113 1.2.3. Chained Directory Protocols......Page 114 2.1. Extended Pointer Schemes......Page 115 2.2. The University of Pisa Protocols......Page 117 3. About the Research of the Author and His Associates......Page 118 1. Basic Issues......Page 119 1.1. The Mechanisms of a DSM System and Their Implementation......Page 120 1.3. The Granularity of Consistency Maintenance......Page 121 1.4. The Access Algorithms of a DSM System......Page 122 1.6. The Cache Consistency Protocols of a DSM System......Page 123 1.7. The Memory Consistency Protocols of a DSM System......Page 124 1.7.1. Release Consistency......Page 126 1.7.2. Lazy Release Consistency......Page 127 1.7.3. Entry Consistency......Page 128 1.7.4. Automatic Update Release Consistency......Page 129 1.7.5. Scope Consistency......Page 131 1.8. A Special Case: Barriers and Their Treatment......Page 132 1.9. Existing Systems......Page 133 1.10. New Research......Page 135 2. Advanced Issues......Page 136 3. About the Research of the Author and His Associates......Page 139 EPILOGUE......Page 141 1. Introduction......Page 143 2.1. Transmitter Design......Page 144 2.2. Receiver Design......Page 146 3. Medium-Speed Data Modem Based on a Single Processor......Page 149 3.1. Transmitter Design......Page 150 3.2. Receiver Design......Page 155 4. Medium-Speed Multimicroprocessor Data Modemfor High Frequency Radio......Page 162 4.2. Receiver Design......Page 164 5. Experiences Gained and Lessons Learned......Page 166 1. Introduction......Page 168 2. GaAs Systolic Array Based on 4096 Node Processor Elements......Page 169 3. Experiences Gained and Lessons Learned......Page 171 1. Introduction......Page 173 2. A Board Which Turns PC into a DSM NodeBased on the RM Approach......Page 174 3. Experiences Gained and Lessons Learned......Page 176 RESEARCH PRESENTATIONMETHODOLOGY......Page 177 1. Introduction......Page 179 3. Structure of the Abstract......Page 180 5. Structure of the Figures and/or Tablesand the Related Captions......Page 181 7. Structure of the Written Paperand the Corresponding Oral Presentation......Page 182 8. Semantics-Based Layout of Transparencies......Page 184 11. Acknowledgments......Page 185 13. Epilogue......Page 186 2. Preparing the Transparencies......Page 190 3. Using the Transparencies......Page 191 6. References......Page 192 REFERENCES......Page 199 ABOUT THE AUTHOR......Page 215 Selected Industrial Cooperation with US Companies (since 1990)......Page 217 Selected Publications in IEEE Periodicals (since 1990)......Page 218 Textbook Citations......Page 221 A Short Biosketch of the Author......Page 223