Embedded Microprocessor System Design using FPGAs

This textbook for courses in Embedded Systems introduces students to necessary concepts, through a hands-on approach. It gives a great introduction to FPGA-based microprocessor system design using state-of-the-art boards, tools, and microprocessors from Altera/Intel® and Xilinx®. HDL-based designs (soft-core), parameterized cores (Nios II and MicroBlaze), and ARM Cortex-A9 design are discussed, compared and explored using many hand-on designs projects. Custom IP for HDMI coder, Floating-point operations, and FFT bit-swap are developed, implemented, tested and speed-up is measured. Downloadable files include all design examples such as basic processor synthesizable code for Xilinx and Altera tools for PicoBlaze, MicroBlaze, Nios II and ARMv7 architectures in VHDL and Verilog code, as well as the custom IP projects. Each Chapter has a substantial number of short quiz questions, exercises, and challenging projects. * Explains soft, parameterized, and hard core systems design tradeoffs; * Demonstrates design of popular KCPSM6 8 Bit microprocessor step-by-step; * Discusses the 32 Bit ARM Cortex-A9 and a basic processor is synthesized; * Covers design flows for both FPGA Market leaders Nios II Altera/Intel and MicroBlaze Xilinx system; * Describes Compiler-Compiler Tool development; * Includes a substantial number of Homework’s and FPGA exercises and design projects in each chapter. Preface Acknowledgments Contents Chapter 1: Embedded Microprocessor Systems Basics 1.1 Introduction Fundamental Microprocessors Aspects 1.2 Embedded Microprocessor on FPGAs 1.3 Microprocessor Instruction Set Design Addressing Modes Data Flow Architectures Comparison of Zero-, One-, Two-, and Three-Address CPUs Register File and Memory Architecture Operation Support Next Operation Location 1.4 FPGA Technology Classification by Granularity Classification by Technology Benchmark for FPLDs Recent FPGA Families and Features FPGAs Competing Technology 1.5 Design with Intellectual Property Cores IP Core Comparison and Challenges IP Core-Based PLL Design Example Review Questions and Exercises Short Answer Fill in the Blank True or False Projects and Challenges References Chapter 2: FPGA Devices, Boards, and Design Tools 2.1 Introduction 2.2 Selection of Prototype Board Memory Basic I/O Components Display Options Analog Interface Communication 2.3 FPGA Structure Xilinx FPGA Architecture Overview The ZyBo Xilinx Z-7010 Device Logic Resources XC7Z010-1CLG400C Altera FPGA Architecture Overview The Altera EP5CSEMA5F31C6 Logic Resources EP5CSEMA5F31C6 Additional Resources and Routing EP5CSEMA5F31C6 2.4 Case Study: A PSM Called URISC The URISC Processor Model Design Compilation in Altera Quartus Design Compilation in Xilinx Vivado Design Tool Considerations for Simulation Altera-Specific Simulation Consideration Xilinx-Specific Simulation Consideration Writing Test Benches Quartus Floor Planning Vivado Floor Planning Timing Estimates and Performance Analysis Review Questions and Exercises Short Answers Fill in the Blank True or False Projects and Challenges References Chapter 3: Microprocessor Component Design in VHDL 3.1 Introduction 3.2 Lexical Elements 3.3 Operators and Assignments 3.4 Data Types, Data Objects, and Attributes VHDL Data Types Conversion Functions Attributes Data Objects 3.5 VHDL Statements and Design Coding Recommendations Combinational Coding Recommendations Basic Sequential Circuit Coding: Flip-Flop and Latches Memory Finite State Machine Design Hierarchy and Components VHDL Coding Style, Resources, and Common Errors 3.6 Further Readings Review Questions and Exercises Short Answer Fill in the Blank True or False Projects and Challenges References Chapter 4: Microprocessor Component Design in Verilog 4.1 Introduction 4.2 Lexical Elements 4.3 Operators and Assignments 4.4 Data Types and Value Set Verilog Values Set Verilog Data Types 4.5 Verilog Statements and Design Coding Recommendations Combinational Coding Recommendations Basic Sequential Circuit Coding: Flip-Flop and Latches Memory Finite-State Machine Design Hierarchy and Components Verilog Coding Style, Resources, and Common Errors 4.6 Further Reading Review Questions and Exercises Short Answer Fill in the Blank True or False Projects and Challenges References Chapter 5: Microprocessor Programming in C/C++ 5.1 Introduction 5.2 Lexical Elements 5.3 Data Types, Data Attributes, and Storage Class Basic C Data Types 5.4 C-Operators and Assignments 5.5 Control Flow Constructs 5.6 Code Hierarchy and I/O 5.7 Additional Considerations and Recommendations Debugger Versus Debug Printing C Versus C++ Performance Evaluation of Microprocessor Systems 5.8 Further Readings Review Questions and Exercises Short Answer Fill in the Blank True or False Projects and Challenges References Chapter 6: Software Tool for Embedded Microprocessor Systems 6.1 Introduction 6.2 Assembler Development and Lexical Analysis 6.3 Parser Development 6.4 SW Debugger and Instruction Set Simulator Review Questions and Exercises Short Answer Fill in the Blank True or False Projects and Challenges References Chapter 7: Design of the PicoBlaze Softcore Microprocessor 7.1 Introduction 7.2 Overview Kcpsm6 Instruction Set 7.3 Initial PicoBlaze Synthesizable Architecture 7.4 PicoBlaze Synthesizable Architecture with Scratchpad Memory 7.5 PicoBlaze Synthesizable Architecture with Link Control Review Questions and Exercises Short Answer Fill in the Blank True or False Projects and Challenges References Chapter 8: Software Tools for the PicoBlaze Softcore Microprocessor 8.1 Introduction 8.2 The KCPSM6 Assembler 8.3 Instruction Set Simulator for the PicoBlaze 8.4 C-Compiler for the PicoBlaze Data Types in Pccomp Pccomp Operation Support Control Flow Options in Pccomp Functions Call in Pccomp Additional Pccomp Features and Recommendations Review Questions and Exercises Short Answer Fill in the Blank True or False Projects and Challenges References Chapter 9: Altera Nios Embedded Microprocessor 9.1 Introduction 9.2 Top-Down Nios II System Design 9.3 Bottom-Up Nios II System Design 9.4 Custom Instruction Nios II System Design Floating-Point Number Formats and Operations Floating-Point Operations HDL Synthesis Floating-Point Algorithms Design Example: FECG Custom Floating-Point Hardware Options for Nios II Creation and Integration of Custom Logic Block 9.5 Looking Under the Hood: Nios II Instruction Set Architecture HDL Implementation and Testing Synthesis Results for Trisc3n Review Questions and Exercises Short Answer Fill in the Blank True or False Projects and Challenges References Chapter 10: Xilinx MicroBlaze Embedded Microprocessor 10.1 Introduction 10.2 Top-Down MicroBlaze System Design 10.3 Bottom-Up MicroBlaze System Design 10.4 Custom Instruction MicroBlaze System Design DVI and HDMI Display Options Implementation TMDS Encoding and Decoding HDMI Encoder Text Terminals and Font Design HDMI Encoder in HDL CIP Interface for HDMI Encoder Synthesis Results for HDMI Encoder 10.5 Looking Under the Hood: MicroBlaze Instruction Set Architecture HDL Implementation and Testing Synthesis Results and ISA Lesson Learned Review Questions and Exercises Short Answer Fill in the Blank True or False Projects and Challenges References Chapter 11: ARM Cortex-A9 Embedded Microprocessor 11.1 Introduction 11.2 Top-Down ARM System Design 11.3 Bottom-Up ARM System Design 11.4 Custom Instruction ARM System Design Bit-Reverse Application Example and Software Implementation HDL Design of Bit-Swap CIP HW/SW Solution Performance Comparisons 11.5 Looking Under the Hood: ARMv7 Instruction Set Architecture HDL Implementation and Testing Synthesis Results and Lesson Learned Review Questions and Exercises Short Answer Fill in the Blank True or False Projects and Challenges References Appendix A: Verilog Source Code and Xilinx Vivado Simulation Project Files Explained Verilog Project Files URISC Processor Verilog Project Files Trisc2 aka Tiny PicoBlaze RISC Processor Verilog Project Files Trisc3n aka Tiny Nios II RISC Processor Verilog Project Files Trisc3mb aka Tiny MicroBlaze RISC Processor Verilog Project Files Trisc3a aka Tiny ARM Cortex-A9 RISC Processor Appendix B: Glossary Index