Vlsi (hb 2017)

The Process Of Integrated Circuits (ic) Started Its Era Of Vlsi (very Large Scale Integration) In 1970’s When Thousands Of Transistors Were Integrated Into One Single Chip. Nowadays We Are Able To Integrate More Than A Billion Transistors On A Single Chip. However, The Term “vlsi” Is Still Being Used, Though There Was Some Effort To Coin A New Term Ulsi (ultra-large Scale Integration) For Fine Distinctions Many Years Ago. Vlsi Technology Has Brought Tremendous Benefits To Our Everyday Life Since Its Occurrence. Vlsi Circuits Are Used Everywhere, Real Applications Include Microprocessors In A Personal Computer Or Workstation, Chips In A Graphic Card, Digital Camera Or Camcorder, Chips In A Cell Phone Or A Portable Computing Device, And Embedded Processors In An Automobile, Et Al. Vlsi Covers Many Phases Of Design And Fabrication Of Integrated Circuits. For A Commercial Chip Design, It Involves System Definition, Vlsi Architecture Design And Optimization, Rtl (register Transfer Language) Coding, (pre- And Post-synthesis) Simulation And Verification, Synthesis, Place And Route, Timing Analyses And Timing Closure, And Multi-step Semiconductor Device Fabrication Including Wafer Processing, Die Preparation, Ic Packaging And Testing, Et Al. As The Process Technology Scales Down, Hundreds Or Even Thousands Of Millions Of Transistors Are Integrated Into One Single Chip. Hence, More And More Complicated Systems Can Be Integrated Into A Single Chip, The So-called System-on-chip (soc), Which Brings To Vlsi Engineers Ever Increasingly Challenges To Master Techniques In Various Phases Of Vlsi Design. For Modern Soc Design, Practical Applications Are Usually Speed Hungry. For Instance, Ethernet Standard Has Evolved From 10mbps To 10gbps. Now The Specification For 100mbps Ethernet Is On The Way. On The Other Hand, With The Popularity Of Wireless And Portable Computing Devices, Low Power Consumption Has Become Extremely Critical. To Meet These Contradicting Requirements, Vlsi Designers Have To Perform Optimizations At All Levels Of Design. This Book Is Intended To Cover A Wide Range Of Vlsi Design Topics. The Book Can Be Roughly Partitioned Into Four Parts. Part I Is Mainly Focused On Algorithmic Level And Architectural Level Vlsi Design And Optimization For Image And Video Signal Processing Systems. Part Ii Addresses Vlsi Design Optimizations For Cryptography And Error Correction Coding. Part Iii Discusses General Soc Design Techniques As Well As Other Application-specific Vlsi Design Optimizations. The Last Part Will Cover Generic Nano-scale Circuit-level Design Techniques. Preface......Page 3 Hannu Olkkonen and Juuso T. Olkkonen......Page 7 Ibrahim Saeed Koko and Herman Agustiawan......Page 17 Tsung-Han Tsai, Chia-Pin Chen, and Yu-Nan Pan......Page 49 Chih-Hsien Hsia and Jen-Shiun Chiang......Page 75 Ching-Yen Chien, Sheng-Chieh Huang, Chia-Ho Pan and Liang-Gee Chen......Page 105 Ming-Haw Jing, Jian-Hong Chen, Yan-Haw Chen, Zih-Heng Chen and Yaotsu Chang......Page 121 Chiou-Yng Lee......Page 137 Zhongfeng Wang and Xinming Huang......Page 157 Jin Sha, Zhongfeng Wang and Minglun Gao......Page 181 Erik Hertz and Peter Nilsson......Page 205 D. Reisis......Page 227 Arjuna Madanayake and Leonard T. Bruton......Page 253 Kazuhiro Nakamura, Masatoshi Yamamoto, Kazuyoshi Takagi and Naofumi Takagi......Page 279 Chun-Lung Hsu, Yu-Sheng Huang and Chen-Kai Chen......Page 291 Shun-Chieh Lin, Jia-Ching Wang, Jhing-Fa Wang, Fan-Min Li and Jer-Hao Hsu......Page 303 Reza Sabbaghi-Nadooshan, Mehdi Modarressi and Hamid Sarbazi-Azad......Page 323 Houman Zarrabi, Zeljko Zilic, Yvon Savaria and A. J. Al-Khalili......Page 337 Guo Yu and Peng Li......Page 359 Bao Liu......Page 381 Blaise Ravelo, André Pérennec and Marc Le Roy......Page 415 Saïd Bettayeb......Page 441 Ahmed Lakhssassi and Mohammed Bougataya......Page 447 In this chapter, we have studied the first purely CNT and CNFET based nano-architecture, which is based on (1) a novel reconfigurable double gate carbon nanotube field effect transistor (RDG-CNFET) device, (2) a multi-layer CNT crossbar structure with sandwiched via-forming and gate-forming molecules, and (3) a novel voltage-controlled nano-addressing circuit not requiring precise layout design, enabling manufacture of nanoelectronic systems in all existing CMOS circuit design styles. A complete methodology of adaptive configuration of nanoelectronic systems based on the CNT crossbar nano-architecture is also presented, including (1) an adaptive nano-addressing method for the voltage-controlled nano-addressing circuit, (2) an adaptive RDG-CNFET gate matching method, and (3) a set of catastrophic defect mapping methods, which are specific (to