Low Power Networks-on-Chip

Low Power Networks-on-Chip Edited by: (editors) Cristina Silvano Marcello Lajolo Gianluca Palermo In recent years, both Networks-on-Chip, as an architectural solution for high-speed interconnect, and power consumption, as a key design constraint, have continued to gain interest in the design and research communities, since power and energy issues still represent one of the limiting factors in integrating multi- and many-cores on a single chip. This book covers power and energy aware design techniques from several perspectives and abstraction levels and offers a single-source reference to some of the most important design techniques proposed in the context of low-power design for networks-on-chip architectures. •Describes the most important design techniques that were invented, proposed, and applied to reduce both dynamic power and static power dissipation in networks-on-chip based architectures; •Applies state-of-the-art, low-power design techniques to the design of Networks-on-Chip, to demonstrate methodology for design of high-speed, low-power interconnect; •Offers a single source reference to the latest research, otherwise available only in disparate journals and conference proceedings 7.2 Related Work......Page 3 10.5.1 On-Chip Multi-Carrier Generation......Page 7 9.3.3 Photonic Network Fundamentals......Page 13 3.3.3 Performance Evaluation......Page 15 9.4 Corona: A Nanophotonic Case Study......Page 17 Cover......Page 1 10.2 Interconnect Problem in Future Information Processor......Page 2 Low Power Networks-on-Chip......Page 4 9.2.1 Overview......Page 5 Preface......Page 8 9.3.2 Optical Interconnect......Page 11 9.2.2 Sources......Page 6 10.5.2 On-Chip RF-Interconnect......Page 9 9.3.1 Electrical Interconnects......Page 10 8.6 Extension for 3D ICs......Page 12 About the Editors......Page 14 10.7 Future RF-I Research Direction......Page 19 References......Page 20 Part I Low-Level Design Techniques......Page 22 Contents......Page 16 Contributors......Page 18 8.7.4 Analysis of Results......Page 21 1.1 Network on-Chip: Past, Present, and the Future......Page 23 1.1.1.2 Rings......Page 24 1.1.1.3 Meshes......Page 25 1.2.1 Circuit-Switched Data with Packet-Switched Arbitration NoC......Page 27 4.10.1 Design of a Simple Synchronizer......Page 28 1.2.2 Circuit Innovations for Circuit/Packet Switched Network Arbitration......Page 30 5.6.1 Generic Router Architecture......Page 31 5.6.2 Area and Power Dissipation......Page 32 1.2.3 Data Transmission Circuit Innovations......Page 33 References......Page 36 5.6.3 Energy Consumption......Page 34 1.3 NoC Measurements and Tradeoffs in 45nm CMOS......Page 35 9.5 Summary......Page 29 1.1.2.2 Heterogeneity......Page 26 References......Page 39 2.1 Introduction......Page 41 2.2.1 Target Router Architecture......Page 42 2.2.2 Power Analysis of the Target Router Architecture......Page 44 2.3.1 Voltage and Frequency Scaling Techniques......Page 45 2.3.2.2 Fine-Grained Power Gating Techniques......Page 46 2.3.2.3 Power Gating for Interconnection Networks......Page 47 2.4.1 Power Domain Partitioning......Page 48 2.4.2 Power Domain Implementation......Page 49 2.4.3 Wakeup Latency Estimation......Page 50 2.5.1 Wakeup Latency Impact......Page 51 2.5.2 Look-Ahead Method......Page 52 2.5.3 Look-Ahead with Ever-On Method......Page 54 2.6.1 Simulation Environment......Page 55 2.6.2 Performance Impact......Page 57 2.6.3 Leakage Power Reduction......Page 59 2.7 Summary......Page 60 References......Page 62 3.1 Introduction......Page 64 3.2.1 Metrics for Energy Efficiency......Page 65 3.2.2.2 Frequent Value Coding......Page 66 3.2.2.3 Crosstalk Avoidance Coding......Page 67 3.2.3.1 Low-Swing Signaling......Page 68 3.2.3.2 Differential Signaling......Page 69 3.2.3.4 Dual-Voltage Buffers......Page 70 3.2.3.7 Globally Asynchronous Locally Synchronous (GALS) Signaling......Page 71 3.2.4.2 Combining Error Control Coding with Adaptive Voltage Scaling......Page 72 3.3 Lookahead-Based Transition-Aware Link Voltage Control......Page 73 3.3.1 Lookahead Transmitter Design......Page 74 3.3.2 HI/LO Voltage Selection......Page 77 3.3.3 Performance Evaluation......Page 78 3.3.3.1 Comparison with Traditional Two-Inverter Driver......Page 79 3.3.3.2 Comparison with Adaptive Voltage Driver......Page 81 3.3.3.3 Comparison with Prior Dual-Voltage Switching Method......Page 83 3.3.4 Limitations......Page 84 References......Page 86 Chapter 4 Asynchronous Communications for NoCs......Page 89 4.1 Introduction......Page 90 4.1.1 Variability......Page 91 4.1.2 Power Consumption......Page 92 4.1.3 Chapter Structure......Page 93 4.2 History of Asynchronous Communications Before the NoC Era......Page 94 4.3 Token-Based View of Communication......Page 95 4.4.1 Signalling Techniques......Page 97 4.4.2 Handshake Protocols......Page 98 4.4.3 Channel Types......Page 99 4.5.1 Dual-rail......Page 100 4.5.2 1-of-N and M-of-N......Page 101 4.5.3 Single Transition Codes......Page 104 4.6.1 Bundled-Data Encoding......Page 105 4.6.2 Single-Track Signalling......Page 106 4.7.1 Phase Encoding......Page 107 4.7.2 Data-Reference Codes......Page 108 4.7.3 Summary on Codes......Page 109 4.8 Pipelining......Page 110 4.8.1 Paired Handshake......Page 111 4.8.2 Serial vs. Parallel Links......Page 112 4.9 Networks-on-Chip......Page 113 4.10 Synchronizers......Page 115 4.10.1 Design of a Simple Synchronizer......Page 116 4.11 Routers......Page 118 4.11.1 Arbiters......Page 119 4.12.1 Logic Synthesis......Page 120 4.12.2 Syntax-Driven Design......Page 121 References......Page 124 Part II System-Level Design Techniques......Page 128 5.1 Introduction......Page 129 5.2.1 Classification of Routing Algorithms......Page 131 5.2.2 Wormhole Switching and Deadlock......Page 132 5.2.3.1 Routing Function......Page 133 5.2.3.2 Selection Function......Page 134 5.2.4 Routing Logic and Hardware Implications......Page 135 5.2.5 Region Concept in NoC......Page 136 5.2.6 Network Energy and Routing Algorithms......Page 137 5.2.7 Common Performance Metrics......Page 138 5.3.2 Channel Dependency Graph and Deadlock Freedom......Page 139 5.3.3 Application-Specific Channel Dependency Graph......Page 140 5.3.4 Routing Adaptivity......Page 141 5.4.2 Main Algorithm......Page 144 5.4.4.1 Routing Table Compression......Page 147 5.5.1 Traffic Scenarios......Page 149 5.5.2 Adaptivity Analysis......Page 151 5.5.3 Simulation Based Evaluation......Page 152 5.5.3.1 Homogeneous 2D Mesh NoC......Page 153 5.5.3.2 NonHomogeneous 2D Mesh NoC with Regions......Page 155 5.6.1 Generic Router Architecture......Page 159 5.6.2 Area and Power Dissipation......Page 160 5.6.3 Energy Consumption......Page 162 5.7 Conclusions......Page 163 References......Page 164 6.1 Introduction......Page 167 6.2 Related Work......Page 169 6.3.1 On-Chip Network Architecture......Page 170 6.3.2 Compression Support......Page 172 6.3.3 Table Organization......Page 174 6.4.3 Increasing Compression Effectiveness......Page 176 6.5 Methodology......Page 178 6.6 Experimental Results......Page 179 6.6.1 Compressibility and Value Pattern......Page 180 6.6.2 Effect on Power Consumption......Page 182 6.6.3 Effect on Packet Latency......Page 184 6.6.4 Compression Table Area Analysis......Page 186 6.6.5 Comparison with Wide/Long-Channel Networks......Page 187 6.7 Conclusion......Page 188 References......Page 189 7.1 Introduction......Page 191 7.2 Related Work......Page 193 7.3 The Target Application......Page 194 7.4 NoC Design and Optimization......Page 197 7.4.1 Cost-Optimized Mapping......Page 198 7.4.2 Setting Link Capacities......Page 200 7.5 Experimental Results......Page 203 7.5.1 Target Router Architecture......Page 204 7.5.2 Synthesis Results......Page 206 7.6 Summary and Conclusions......Page 209 References......Page 210 Part III Future and Emerging Technologies......Page 212 8.1 Introduction......Page 213 8.2.1 2D SoC Architecture......Page 216 8.3 3D SoC Architecture......Page 218 8.4.1 Synthesis Problem Formulation......Page 219 8.5 Synthesis Algorithm for 2D ICs with VI Shutdown......Page 220 8.6 Extension for 3D ICs......Page 224 8.7.1 Design of 2D ICs......Page 225 8.7.2 Baseline Comparison of 2D and 3D ICs......Page 230 8.7.4 Analysis of Results......Page 233 References......Page 234 Chapter 9 CMOS Nanophotonics: Technology, System Implications, and a CMP Case Study......Page 237 9.1 Introduction......Page 238 9.2 CMOS Nanophotonic Technologies......Page 240 9.2.1 Overview......Page 241 9.2.2 Sources......Page 242 9.2.3 Waveguides, Splitters, Couplers and Connectors......Page 243 9.2.4 Detectors......Page 244 9.3 Nanophotonic Network Principles......Page 245 9.3.1 Electrical Interconnects......Page 246 9.3.2 Optical Interconnect......Page 247 9.3.3 Photonic Network Fundamentals......Page 249 9.3.4 Optical Arbitration......Page 250 9.3.5 Optical Barriers......Page 252 9.4 Corona: A Nanophotonic Case Study......Page 253 9.4.1 Corona Architecture......Page 254 9.4.2 Experimental Setup......Page 261 9.4.3 Performance Evaluation......Page 263 9.5 Summary......Page 265 References......Page 266 10.1 Introduction......Page 269 10.2 Interconnect Problem in Future Information Processor......Page 270 10.3 How Can RF Help?......Page 272 10.5.1 On-Chip Multi-Carrier Generation......Page 275 10.5.2 On-Chip RF-Interconnect......Page 277 10.5.3 3D IC RF-Interconnect......Page 284 10.6 Impact of RF-I in Future SoC/NoC Architecture......Page 286 10.7 Future RF-I Research Direction......Page 287 References......Page 293 Index......Page 295