ASIC and FPGA verification : a guide to component modeling

Contents......Page 4 PART I INTRODUCTION......Page 18 1.1 Why Models are Needed......Page 19 1.2 Definition of a Model......Page 21 1.4 How Models Fit in the FPGA/ASIC Design Flow......Page 26 1.5 Where to Get Models......Page 29 1.6 Summary......Page 30 2.1 Formatting......Page 31 2.2 Standard Interfaces......Page 33 2.3 Model Delays......Page 34 2.4 VITAL Additions......Page 35 2.5 Interconnect Delays......Page 41 2.6 Finishing Touches......Page 43 2.7 Summary......Page 47 PART II RESOURCES AND STANDARDS......Page 49 3.1 STD_LOGIC_1164......Page 50 3.2 VITAL_Timing......Page 52 3.3 VITAL_Primitives......Page 54 3.4 VITAL_Memory......Page 56 3.5 FMF Packages......Page 57 3.6 Summary......Page 60 4.1 Overview of an SDF File......Page 62 4.2 SDF Capabilities......Page 67 4.3 Summary......Page 73 5.1 Level 0 Guidelines......Page 74 5.2 Level 1 Guidelines......Page 78 5.3 Summary......Page 85 6.1 Delay Types and Glitches......Page 87 6.3 Pin-to-Pin Delays......Page 89 6.4 Path Delay Procedures......Page 90 6.5 Using VPDs......Page 96 6.7 Device Delays......Page 97 6.8 Backannotating Path Delays......Page 102 6.9 Interconnect Delays......Page 103 6.10 Summary......Page 104 7.1 Advantages of Truth and State Tables......Page 105 7.2 Truth Tables......Page 106 7.3 State Tables......Page 111 7.4 Reducing Pessimism......Page 114 7.5 Memory Tables......Page 115 7.6 Summary......Page 120 8.1 The Purpose of Timing Constraint Checks......Page 121 8.2 Using Timing Constraint Checks in VITAL Models......Page 122 8.3 Violations......Page 135 8.4 Summary......Page 136 PART III MODELING BASICS......Page 137 9.1 Anatomy of a Flip-Flop......Page 138 9.2 Anatomy of a Latch......Page 150 9.3 Summary......Page 159 10.1 Conditional Delays in VITAL......Page 160 10.2 Conditional Delays in SDF......Page 162 10.3 Conditional Delay Alternatives......Page 163 10.4 Mapping SDF to VITAL......Page 165 10.5 Conditional Timing Checks in VITAL......Page 166 10.6 Summary......Page 169 11.1 How Negative Constraints Work......Page 170 11.2 Modeling Negative Constraints......Page 171 11.3 How Simulators Handle Negative Constraints......Page 189 11.4 Ramifications......Page 190 11.5 Summary......Page 191 12.1 Anatomy of a Timing File......Page 192 12.2 Separate Timing Specifications......Page 195 12.4 Custom Timing Sections......Page 196 12.6 Generating SDF Files......Page 197 12.7 Backannotation and Hierarchy......Page 198 12.8 Summary......Page 200 PART IV ADVANCED MODELING......Page 201 13.1 Using VITAL to Simulate Your RTL......Page 202 13.2 The Basic Wrapper......Page 203 13.4 Modeling Delays in Designs with Internal Clocks......Page 217 13.5 Caveats......Page 218 13.6 Summary......Page 219 14.1 Memory Arrays......Page 220 14.2 Modeling Memory Functionality......Page 222 14.3 VITAL_Memory Path Delays......Page 242 14.4 VITAL_Memory Timing Constraints......Page 243 14.5 PreLoading Memories......Page 246 14.6 Modeling Other Memory Types......Page 249 14.7 Summary......Page 260 15.1 Component Models and Netlisters......Page 261 15.3 Generics Passed from the Schematic......Page 263 15.4 Integrating Models into a Schematic Capture System......Page 264 15.5 Using Models in the Design Process......Page 266 15.6 Special Considerations......Page 272 15.7 Summary......Page 276 16.1 Differential Inputs......Page 278 16.2 Bus Hold......Page 288 16.3 PLLs and DLLs......Page 291 16.4 Assertions......Page 293 16.6 State Machines......Page 294 16.7 Mixed Signal Devices......Page 297 16.8 Summary......Page 303 17.1 About Testbenches......Page 304 17.2 Testbench Styles......Page 305 17.3 Using Assertions......Page 306 17.4 Using Transactors......Page 307 17.5 Testing Memory Models......Page 310 17.6 Summary......Page 317 C......Page 318 D......Page 319 M......Page 320 N......Page 321 S......Page 322 T......Page 323 V......Page 324 Z......Page 325 Richard Munden demonstrates how to create and use simulation models for verifying ASIC and FPGA designs and board-level designs that use off-the-shelf digital components. Based on the VHDL/VITAL standard, these models include timing constraints and propagation delays that are required for accurate verification of todays digital designs. ASIC and FPGA Verification: A Guide to Component Modeling expertly illustrates how ASICs and FPGAs can be verified in the larger context of a board or a system. It is a valuable resource for any designer who simulates multi-chip digital designs. *Provides numerous models and a clearly defined methodology for performing board-level simulation. *Covers the details of modeling for verification of both logic and timing. *First book to collect and teach techniques for using VHDL to model "off-the-shelf" or "IP" digital components for use in FPGA and board-level design verification