Advanced Techniques in Logic Synthesis, Optimizations and Applications

Advanced Techniques in Logic Synthesis, Optimizations and Applications Edited by: Sunil P Khatri Kanupriya Gulati This book covers recent advances in the field of logic synthesis and design, including Boolean Matching, Logic Decomposition, Boolean satisfiability, Advanced Synthesis Techniques and Applications of Logic Design. All of these topics are valuable to CAD engineers working in Logic Design, Logic Optimization, and Verification. Engineers seeking opportunities for optimizing VLSI integrated circuits will find this book as an invaluable reference, since there is no existing book that covers this material in a systematic fashion. •Covers the latest research in the areas of Boolean Matching, Logic Decomposition, Boolean Satisfiability •Serves as a single-source reference to key topics in logic synthesis, otherwise only available in disparate publications; •Describes a range of synthesis techniques and Applications of logic design. Front Matter....Pages i-xxi Introduction....Pages 1-6 Front Matter....Pages 7-7 Logic Synthesis by Signal-Driven Decomposition....Pages 9-29 Sequential Logic Synthesis Using Symbolic Bi-decomposition....Pages 31-45 Boolean Factoring and Decomposition of Logic Networks....Pages 47-66 Ashenhurst Decomposition Using SAT and Interpolation....Pages 67-85 Bi-decomposition Using SAT and Interpolation....Pages 87-105 Front Matter....Pages 107-107 Boundary Points and Resolution....Pages 109-127 SAT Sweeping with Local Observability Don’t-Cares....Pages 129-148 A Fast Approximation Algorithm for MIN-ONE SAT and Its Application on MAX-SAT Solving....Pages 149-170 Algorithms for Maximum Satisfiability Using Unsatisfiable Cores....Pages 171-182 Front Matter....Pages 183-183 Simulation and SAT-Based Boolean Matching for Large Boolean Networks....Pages 185-201 Logic Difference Optimization for Incremental Synthesis....Pages 203-225 Large-Scale Boolean Matching....Pages 227-247 Front Matter....Pages 249-249 Algebraic Techniques to Enhance Common Sub-expression Extraction for Polynomial System Synthesis....Pages 251-266 Automated Logic Restructuring with a SPFDs....Pages 267-286 Extracting Functions from Boolean Relations Using SAT and Interpolation....Pages 287-307 A Robust Window-Based Multi-node Minimization Technique Using Boolean Relations....Pages 309-334 Front Matter....Pages 335-335 Synthesizing Combinational Logic to Generate Probabilities: Theories and Algorithms....Pages 337-357 Probabilistic Error Propagation in a Logic Circuit Using the Boolean Difference Calculus....Pages 359-381 Digital Logic Using Non-DC Signals....Pages 383-400 Front Matter....Pages 335-335 Improvements of Pausible Clocking Scheme for High-Throughput and High-Reliability GALS Systems Design....Pages 401-417 Back Matter....Pages 419-423